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Altera CPRI IP Core User Manual (220 pages)

Brand: Altera | Category: Measuring instruments | Size: 3.72 MB |

User Guide

CPRI MegaCore Function

Contents

Chapter 5. Testing Features

ContentsContents v

General Description

CPRI IP Core Features

Device Family Support

MegaCore Verification

Release Information

Installation and Licensing

OpenCore Plus Evaluation

2. Getting Started

Specifying Parameters

Simulation Files

Simulating the Design

Supporting the Transceivers

Specifying Constraints

3. Parameter Settings

Operation Mode Parameter

Line Rate Parameter

Enable Autorate Negotiation

Rx Elastic Buffer Depth

Include MAC Block

Include HDLC Block

Mapping Mode

Application Layer Parameters

Words” on page 4–42

4. Functional Description

Architecture Overview

CPRI IP Core Clocks

Clocking Structure

Notes to Table 4–2:

Reset Requirements

MegaCore

Function

MAP Interface Mapping Modes

Basic AxC Mapping Mode

MAP Interface

Note to Table 4–5:

Note to Table 4–6:

Advanced AxC Mapping Modes

MAP Receiver Interface

Notes to Table 4–7:

MAP Receiver in FIFO Mode

MAP Transmitter Interface

Notes to Table 4–10:

MAP Transmitter in FIFO Mode

Auxiliary Interface

AUX Receiver Module

Avalon-ST 32-bit interface

AUX Transmitter Module

Note to Figure 4–19:

MII Transmitter

MII Receiver

CPU Interface

Control Word Order

Transmitting Ethernet Traffic

Receiving Ethernet Traffic

Accessing the HDLC Channel

Note to Table 4–15:

Features

Physical Layer Architecture

Receiver

High-Speed Transceiver

Rx Elastic Buffer

Descrambling

Frame Synchronization

Alarm Indications

Reset Control Word

Transmitter

Scrambling

Tx Elastic Buffer

External Loopback

CPRI IP Core

Internal Reverse Loopback

Physical Layer Loopback Mode

(1) (2) (3)

MAP Receiver Signals

6–2 Chapter 6: Signals

100

MAP Interface Signals

100

MAP Transmitter Signals

101

6–4 Chapter 6: Signals

102

Auxiliary Interface Signals

103

AUX Receiver Signals

104

AUX Transmitter Signals

105

6–8 Chapter 6: Signals

106

Extended Rx Status Signals

107

CPRI MII Receiver Signals

108

CPRI MII Transmitter Signals

108

CPU Interface Signals

109

CPRI Data Signals

110

Layer 1 Error Signal

111

Autorate Negotiation Signals

111

6–14 Chapter 6: Signals

112

Physical Layer Signals

112

Transceiver Signals

113

6–16 Chapter 6: Signals

114

Note to Table 6–14:

115

6–18 Chapter 6: Signals

116

7. Software Interface

117

Note to Table 7–5:

119

CPRI_HW_RESET

123

Requirements” on page 4–11

123

Note to Table 7–13:

124

Note to Table 7–16:

125

Note to Table 7–17:

126

Note to Table 7–20:

126

Notes to Table 7–21:

127

Notes to Table 7–28:

130

Notes to Table 7–29:

130

Note to Table 7–32:

133

Note to Table 7–33:

133

Note to Table 7–34:

133

Note to Table 7–35:

134

Note to Table 7–36:

134

Notes to Table 7–37:

135

Notes to Table 7–38:

135

Notes to Table 7–39:

136

Notes to Table 7–40:

136

Note to Table 7–45:

137

Ethernet Registers

138

HDLC Registers

143

Note to Figure 8–1:

150

Test Sequence

151

Running the Testbench

153

A. Initialization Sequence

155

Negotiation

157

Notes for Figure B–1:

158

Running Autorate Negotiation

159

Notes to Table C–3:

167

D. Advanced AxC Mapping Modes

173

Fifteen-Bit Width Mode

175

Sixteen-Bit Width Mode

176

Note to Figure D–2:

177

Delay Requirements

179

RE SlaveREC Master

180

Rx Path Delay

181

Most CPRI IP Core Variations

181

Single-Hop Delay Measurement

182

Notes to Table E–1:

183

Notes to Table E–2:

184

Notes to Table E–3:

186

Arria V GT 9.8 Gbps

188

Notes to Table E–4:

189

Tx Path Delay

190

Note to Table E–6:

192

T_txv_TX

194

in Figure E–1 on page E–2

194

Round-Trip Delay

196

Round-Trip Cable Delay

196

Families

202

Round-Trip Delay Calculation

205

Multi-Hop Delay Measurement

206

Additional Information

213

Document Revision History

214

How to Contact Altera

218

Typographic Conventions

218

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